1. Technical Field
The present invention relates to uses for a boundary-scan or Joint Test Action Group (JTAG) interface port of an integrated circuit (IC). Further, the present invention relates to wireless network communications using an IC having a JTAG interface.
2. Related Art
Today numerous protocols exist that allow multiple devices to communicate with one another over a wireless link (e.g. 802.11/Wi-Fi, Wi-Max, Bluetooth, UltraWideband (UWB), 802.15.4/ZigBee). Wireless networks blanket the country providing access to mobile phone users and users of digital devices, such as lap top computers. The trend in electronics has been to remove cables wherever possible in favor of wireless communication systems.
One communication interface that continues to use a cable instead of a wireless connection, however, is a JTAG port. A JTAG port is a four-wire interface primarily used for system testing and debugging of an integrated circuit (IC). Two defining specifications for JTAG are IEEE 1149.1 and IEEE 1532. The IEEE 1149.1 boundary-scan standard defines an interface for accessing multiple ICs that are serially interconnected on a printed circuit board.
All ICs do not include JTAG ports, but Programmable Logic Devices (PLDs), such as Field Programmable Gate Arrays (FPGAs) and Complex PLDs (CPLDs), are user programmable circuits that typically do include JTAG ports. JTAG headers can be found on most PLD development boards, providing a universal means of communicating with the PLD and other on-board devices. Other devices, such as microprocessors and Digital Signal processors (DSPs), sometimes also include JTAG ports. Because PLDs typically include a JTAG port, the JTAG interface has more recently been developed as a programming interface that provides a readily available programming link to the configuration memory of the PLD, as well as a communication link to the PLD for other purposes.
One FPGA manufacturer, Xilinx Incorporated of San Jose, Calif., provides tools that use the JTAG boundary-scan chain for functions such as testing and debugging, as well as for configuration or programming. For example ChipScope PRO uses JTAG for real-time debugging, EDK provides in-system processor debugging, System Generator for DSP (Sysgen) provides a tool available for high-level modeling and simulation, and iMPACT provides for configuration of programmable devices. These tools currently communicate to FPGA and CPLD devices via a programming cable (e.g., MultiLINX, Parallel Cable III, Parallel Cable IV). One end of the cable connects to the PLD development board and the other end connects to the host PC running application software.
Communication with an IC having a dedicated JTAG port is described with reference to the components of FIG. 1. Communication uses the JTAG interface 4 of a component 2, such as a PLD, to communicate with a host PC 6 having a JTAG communication port. Communication uses the JTAG interface components, including the Boundary Scan Chain (BSC) elements 10 and JTAG port 7 of the component 2 as a serial interface with the JTAG port of the host PC component 6. Data is provided serially between the primary Test Data Input (TDI) pin and the primary Test Data Output (TDO) pin of the JTAG access port 7. The Test Access Port (TAP) controls data flow and receives JTAG control signals from the Test Mode Select (TMS) and Test Clock (TCK) inputs.
For a single device 2, data is shifted is shifted around in the BSC elements 10 so that individual logic values appear on each of the I/O pins 12. The logic values are shifted into the component 2 using the four-wire JTAG interface 4. Data must be shifted into all input/output (I/O) pin locations 12 for every new I/O vector applied. In other words, to toggle a single output pin requires writing values and shifting them into all the I/O locations requiring a number of JTAG clock cycles to transfer a complete set of data. To monitor logic values applied to one of the I/O pins, the data can be shifted back through the JTAG boundary scan chain and out the TDO port. Data can similarly be shifted through the boundary scan of multiple ICs having JTAG ports linked or daisy chained together by cables.
For some design requirements, cables can be undesirable. Cables impose fixed structures linked with the boundary scan topology. Daisy chaining to link together the JTAG ports of multiple devices using cables is awkward as an adapter must be used to connect TDO to TDI pins between boards. Cables further restrict the physical distance between boards to the length of the cable.